Principal Interconnect Architect - Chisel/TileLink IP

SiFive is seeking a principal-level hardware engineer to design industry-leading CPU and interconnect IP, driving the adoption of RISC‐V as the architecture of choice for SOC designs across a broad range of vertical applications. The role emphasizes massively configurable IP and generating hardware as configurable software generators using Chisel. The candidate will architect and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and other infrastructure logic in RTL