Staff CAD Engineer

Key Responsibilities: Execute and contribute to the CAD engineering roadmap for next-gen GPU and SoC designs. Develop and maintain automation scripts, flows, and methodologies for power-efficient design. Support low-power design at scale - including power analysis, optimization, verification, and signoff. Integrate RTL, physical design, and DTCO strategies into cohesive CAD workflows. Debug complex tool and flow issues across the design lifecycle. Partner cross-functionally with internal teams (RTL, physical design, verification) and external EDA vendors. Maintain technical documentation and stay current with emerging GPU and verification technologies. Drive best practices and continuous improvement in a fast-paced, global environment.

Required Skills & Experience: 6+ years of hands-on experience in CAD engineering, design methodology, or design enablement for GPU, CPU, or complex SoC programs. Strong working knowledge of low-power tools and methodologies, including: RTL and gate-level power analysis Power optimization and signoff flows Tools: Prime Power, Power Artist, Empower, Joules, RTL-Architect, or equivalents. Solid understanding of the end-to-end ASIC design flow, including: RTL design, verification, synthesis Physical design, timing, power, EMIR, DTCOHands-on experience with EDA tools from: Synopsys, Cadence, or Mentor Graphics (simulation, synthesis, linting, verification).Working knowledge of EMIR tools and methodologies: Transistor, gate, and package-level analysis Tools: Redhawk, Totem, Voltus, or equivalents. Strong analytical and problem-solving skills - data-driven approach to debugging and optimization. Excellent collaboration and communication skills - ability to navigate ambiguity and take ownership in a global, fast-paced environment. Preferred/

Nice-to-Have: Experience with advanced process nodes (5nm, 3nm, etc.).Familiarity with DTCO (Design Technology Co-Optimization) strategies. Scripting/programming skills (Python, TCL, Perl) for automation. Experience in GPU architecture or high-performance computing designs.