Senior RTL Design Engineer - Space-Grade ASICs for Starlink

SpaceX is seeking a SR. RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink. You will implement RTL in Verilog/SystemVerilog, optimize timing, and collaborate with verification, synthesis, and physical teams to ensure validated silicon bring-up. The role requires 5+ years in RTL, a relevant bachelor’s degree, and experience with high-speed, low-power design techniques and AXI/AHB-style interfaces.