Senior ASIC DV Engineer — Tapeouts, UVM & Power
qualcommSanta Clara, CA
$153,200 - $229,800 per yearAPPLY NOW
Senior ASIC DV Engineer — Tapeouts, UVM & Power
qualcommSanta Clara, CA
3 days ago
Industries
Semiconductor and Related Device ManufacturingSemiconductor Machinery ManufacturingPrinted Circuit Assembly (Electronic Assembly) Manufacturing$153,200 - $229,800 per year
APPLY NOWAbout the role
A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. Please double check you have the right level of experience and qualifications by reading the full overview of this opportunity below. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree or higher in related fields. xmcpwfu This position offers a competitive salary range of $153,200.00- $229,800.00 with additional benefits including a discretionary bonus program.
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JOB OVERVIEW
Salary
$153,200 - $229,800 per year
Experience level
Lead
Location
Santa Clara, CA
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
3 days ago
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