Advanced-Node SoC Physical Design Lead (7/5/3nm)
sk hynix memory solutionsSan Jose, CA
Advanced-Node SoC Physical Design Lead (7/5/3nm)
sk hynix memory solutionsSan Jose, CA
yesterday
Industries
Semiconductor and Related Device ManufacturingElectronic Computer ManufacturingComputer Storage Device ManufacturingAbout the role
SK hynix memory solutions in San Jose seeks a Sr. Staff / Principal Physical Design Engineer to lead high-performance SoC physical implementation from RTL to GDS. You will work closely with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success.
You will mentor junior engineers, define team methodologies, and drive tapeouts across 7nm/5nm/3nm nodes, balancing performance, power, and area in a fast-paced environment.
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JOB OVERVIEW
Experience level
Lead
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday
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