ASIC Design Engineer

What you'll do: Define micro‑architecture and write detailed design specifications. Develop high‑quality, synthesizable RTL in SystemVerilog/Verilog. Integrate in‑house and third‑party IPs; manage SoC interconnect and memory maps. Run and clean Lint, CDC and RDC checks; author UPF for low‑power designs. Support synthesis, timing closure and ECO activities. Collaborate with DV, DFT and PD teams to deliver tape‑out ready designs. What you bringBachelor's or Master's in Electrical/Computer Engineering. Proven RTL design experience on ASIC or SoC projects. Strong understanding of digital design fundamentals, timing and clock domain crossing. Familiarity with Lint/CDC tools (SpyGlass, Questa CDC) and synthesis flows. Experience with bus protocols such as AXI, AHB, APB. Scripting in Python, Perl or Tcl.

Nice to have: Experience with low‑power design (UPF/CPF) and multi‑voltage domains. IP‑XACT based integration flows. Exposure to high‑speed interfaces or processor subsystems. Why I2IntechYou'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.