Senior MBIST Engineer

Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS.Integrate and verify MBIST at the top level. Develop, execute, and debug MBIST simulations using Synopsys VCS, including: RTLNo-delay gate level simulations With-delay (timing-aware) simulations Generate and validate MBIST test patterns using Vecgen. Debug RTL, simulation, and MBIST integration issues. Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure. Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues. Drive issue resolution independently and document implementation flows and debug findings.

Required Qualifications: 8+ years of hands-on DFT experience, with significant focus on MBIST.Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.Proficiency with Synopsys VCS for MBIST verification and simulation.