Senior Physical Design Engineer Memory-Centric SoC

conductorSan Jose, CA

yesterday

Occupations

Microsystems Engineers Computer Hardware Engineers Electronics Engineers, Except Computer

Industries

Semiconductor and Related Device Manufacturing Electronic Computer Manufacturing Printed Circuit Assembly (Electronic Assembly) Manufacturing

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About the role

Samsung Semiconductor in San Jose, CA, seeks a skilled digital physical design engineer to own memory-centric IP and full-chip floorplanning, CTS, and timing closure. You will collaborate with RTL/verification teams, develop TCL/Python flows, and contribute to AI/ML workloads while advancing PPA, power integrity, and tapeout on advanced FinFET nodes. This role offers a competitive US-wide pay range and comprehensive benefits in a collaborative, global environment.

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JOB OVERVIEW

Experience level

Lead

Location

San Jose, CA

Occupation

Microsystems Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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