Senior RTL Architect: Memory Subsystem for AI Chips

Architect, a frontier AI lab for chip design, seeks a Founding Member of the Technical Staff to own the AI-driven memory subsystem RTL design for production silicon. You will shape the microarchitecture, define DDR/HBM controller interfaces, and drive high-bandwidth, low-latency memory paths for ML workloads. Collaborating with DV, SW, and ML teams, you will refine specs, validate timing, and prototype on FPGA platforms while advancing power and area targets for next‑gen accelerators.