Senior Analog & Mixed-Signal Modeling Engineer

Us Tech Solutions in Austin, TX, is seeking a seasoned engineer to build behavioral models of analog and mixed-signal circuits in SystemVerilog, integrating into a UVM verification environment for high-speed SerDes and SoC IP. You will collaborate with analog and RTL teams, define model architecture and accuracy targets, and validate against transistor‑level results, while debugging simulations and documenting interfaces in a fast-paced CMOS process setting.