Senior Verification Lead: SystemVerilog/UVM (Onsite)

A technology consulting firm in Redmond, WA is looking for a Design Verification Lead specializing in SystemVerilog and UVM. The ideal candidate will possess extensive experience in architecting and maintaining UVM testbenches and leading verification teams. Responsibilities include defining verification strategies and collaborating with design teams to ensure quality and efficiency in the silicon development process. This role is crucial for those with a deep understanding of AMBA protocols and a track record in hands-on verification and leadership. Full-time onsite position.