Senior PLL & Analog Designer (RF/Serdes)

Samsung Semiconductor Inc. in San Jose, CA, is seeking a Senior/Staff PLL Designer to develop high-performance PLLs and clocking subsystems for RF transceivers and high-speed I/O in deep-submicron CMOS. You will collaborate with digital and software teams, perform system modeling, verification, and production support, and contribute to layout and lab testing to meet stringent requirements.