Signal Integrity Engineer - DDR4/DDR5

Key Responsibilities: Develop SI/PI methodologies; collaborate on studies and package designs for DDR products. Define specs and requirements (e.g., packaging, PCB routings, decoupling, simulations, jitter analysis) with design/validation teams. Guide design team via SI/PI studies, simulations, and correlations for top SI performance (e.g., optimal RMT scores). Partner with customers on optimal SI/PI solutions. Support debug and lab bring-up.

Qualifications: MS/PhD in Electrical Engineering; 10+ years experience, including DDR4/DDR5 focus. Experience simulating high-speed memory (DDR4/DDR5) and/or SERDES. Strong in EM and transmission line theory. Expertise in equalization (FIR/FFE/DFE/CTLE). Proficient in package/PCB design: editing APD/Allegro files, SI/PI-driven BGA, system simulations. Hands-on correlation of simulations with lab measurements (scopes, TDRs, VNAs).Desirable: Server system knowledge (CPUs to DRAMs); crosstalk/jitter in source-synchronous interfaces for low BER. Skilled in Spice, ADS, HFSS, Q3D/PowerSI. Plus: RedHawk/Totem, XcitePI, Virtuoso familiarity. Valued: Lab experience with passive components, margins, noise (scopes, VNA/TDR).

Preferred: Basic high-speed link circuit knowledge. Excellent communication, writing, presentation skills for customers/teams. Innovative, self-motivated team player with leadership. Benefits Hybrid: 3 days/week in office Compensation: Johns Creek, GA: Base midpoint ~$180K; Bonus 20%; RSUs $80K–$160K. San Jose, CA: Base midpoint ~$210K; Bonus 20%; RSUs $92K–$184K. If you're a technical expert in SI/PI, EM simulation, transmission lines, and lab tools like ADS/HFSS/PowerSI, apply now. Push high-speed memory boundaries with us!