About the role

Google DeepMind in Mountain View seeks a Silicon Engineer, Power Analysis to design and optimize power for production chips. You will architect power solutions, drive RTL power analysis, and integrate power flows across SoC teams to meet performance and efficiency goals.
Required: 7+ years in ASIC power analysis, tape-outs, Verilog, and industry EDA tools (PowerArtist, PrimeTime, Innovus, etc.), plus scripting in Perl or Tcl. Master’s or PhD preferred; strong collaboration skills a must.

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JOB OVERVIEW

Experience level

Senior

Location

Mountain View, CA

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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