Senior Static Timing Engineer – ASIC Timing & Automation

Google is seeking a Senior Static Timing Engineer in Sunnyvale, CA, to lead the physical implementation of high-performance ASICs. You will develop constraints, validate timing, and drive timing closure for large compute chips, collaborating with architecture, logic, and DFT teams. The role requires hands-on STA expertise, scripting in Tcl/Perl/Python, and evaluating tools and vendors to ensure robust sign-off across complex design flows.