Design Verification Engineer

Senior Verification Engineer Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits. Backed by Silicon Valley's top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & Global Foundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents. We are building next- generation tools for silicon design by combining deep verification expertise with modern AI systems. As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams verify chips. If you want to build tools that scale with the new era of complexity in hardware, this role offers high ownership and direct impact on real-world chip development. Own verification strategy across multiple IP blocks and subsystems, from testbench architecture to signoff. Design and develop AI assisted workflows that accelerate verification, coverage closure, and debug. Build reusable verification frameworks using SystemVerilog, UVM, Python and custom automation tooling. Collaborate with ML and software teams to integrate AI models into existing DV environments. Contribute to product direction by exploring how automation can reshape verification methodologies. Work with customers in a forward deployed capacity when needed, translating real design challenges into product features. Drive tapeout readiness with full accountability for quality metrics, regression health, and coverage targets. Mentor junior engineers and help define best practices for next generation verification teams. Opportunity to influence the future of tooling and AI guided verification flows. High ownership from day one including technical decisions, roadmap input, and customer interactions. Exposure to both engineering and product thinking. Fast- moving environment built for builders who take initiative rather than wait for direction.4 to 6 years of hands-on verification experience. Strong SystemVerilog and UVM skills with proven debug depth. Familiarity with Python or similar scripting languages. Curious mindset toward AI or automation in verification, even if not an expert yet. Ability to work across domains and communicate clearly with software or ML teams. Comfortable interacting with clients, architects, and leadership when needed. Thrives in a high responsibility environment and enjoys creating solutions that did not exist before. Experience with formal verification, co-simulation or stimulus generation frameworks. Background in ML, LLMs, data pipelines, or tool development. Previous involvement in customer facing or forward deployed engineering roles. Demonstrated ability to build tools that others actually use.