ASIC Physical Design

Location: San Jose, CA (onsite)

Job Type: W2 Contract Interview Process: 1 phone, 1 panel onsite (zoom option) Skills/JD: Physical Design engineer to own the entire block Floorplanning, Placen Route, Timing Closure DRC/LVS checks Low nm experience preferred Cadence tooling - They are using Innovus and Voltus mostly Synopsys tools for Timing Analysis job requirements below: Good understanding of Cadence tools (Innovous, Quantus, Voltus). Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route. Experience in developing and implementing Power-grid and high speed clock constraints and specifications. Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level. Experience with CDC, static timing analysis methodologies and relevant tools. Understanding and experience of mixed signal environments is a must.