Senior SoC Verification Architect

Mirafra Technologies invites an architect-level verification engineer to build block and full-chip environments for SOCs with embedded CPUs and mixed-signal interfaces. You will develop test plans, create C/SV/UVM tests, and debug RTL/gate simulations alongside design engineers. Diagnostics for FPGA prototypes and ASIC validation are included in this role. You will replicate silicon bugs in simulation, convert tests to test patterns for ATE bringup, and evaluate new verification methodologies