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About the role

Overview: In this role, you will contribute to large-scale ASIC implementations using latest technology nodes. You will lead design-closure activities within a multidisciplinary team and adapt to diverse EDA tools to meet quality targets. You’ll collaborate across global customers and design teams to drive successful silicon outcomes. This position offers impact in shaping complex digital designs and advancing Broadcom’s leadership in semiconductor solutions. Compensation / Benefits Medical, dental and vision plans 401(K) with company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP) paid holidays, sick leave and vacation Paid Family Leave
Responsibilities: Participate in large, complex design implementations across technology nodes Lead one or more design-closure disciplines within the team Apply and adapt to multiple EDA vendor solutions Drive peer reviews to ensure quality requirements are met Collaborate with customers and global design teams
Key requirements: Bachelor or higher with 12+ years of related experience, or Master with 10+ years, or PhD with 7+ years expertise in synthesis, design-for-test, floorplanning, place-and-route, clock methodology, power planning and analysis, timing closure, signal integrity, and physical design checks ability to work on complex technical projects and lead efforts with minimal supervision experience with multiple EDA tools and adapting to changing requirements leadership cross-functional collaboration strong communication synthesis design-for-test (DFT) floorplanning

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JOB OVERVIEW

Experience level

Lead

Location

San Jose, CA

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

today

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