Staff SoC Verification Architect

Efficient Computer in San Francisco is seeking an experienced Staff Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This role offers ownership of verification challenges, exposure to edge and data center scale, and collaboration with software teams pre-silicon; a strong background in UVM, System Verilog, Python, and C/C++ is required, with 10+ years of experience.