Senior SRAM IC Layout Engineer – Advanced CMOS (5nm/3nm)
rose internationalSanta Clara, CA
Senior SRAM IC Layout Engineer – Advanced CMOS (5nm/3nm)
rose internationalSanta Clara, CA
today
Industries
Semiconductor and Related Device ManufacturingElectronic Computer ManufacturingSemiconductor Machinery ManufacturingAbout the role
Rose International seeks a Senior SRAM Custom IC Layout Design Engineer in Santa Clara, CA, onsite for a 12-month engagement supporting NVIDIA. The role focuses on complete custom layout of SRAM bitcell arrays, memory periphery, and related macros using advanced CMOS processes.
You will lead floorplanning, DRC/LVS checks with Cadence Virtuoso and Calibre, collaborate with circuit design and PnR teams, ensure layout quality, density, and reliability targets, and mentor junior engineers while
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JOB OVERVIEW
Experience level
Senior
Location
Santa Clara, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
today
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