Senior UVM Design Verification

Job Type: Contract

Duration: 6+ Months

Location: Onsite in San Jose, CARequirement:8+ years of relevant experience We are seeking an experienced Senior ASIC Design Verification Engineerto lead verification efforts for advanced AI and compute chiplet technologies. In this role, you’ll architect, build, and execute comprehensive verification environments from the ground up — ensuring performance, reliability, and scalability across high-performance fabric and interconnect systems. You’ll work closely with cross-functional teams across design, architecture, and firmware to validate cutting‑edge SoC designs used in next‑generation AI platforms.

Responsibilities: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.7–10+ yearsof hands‑on experience in ASIC or SoCdesign verification. Proven expertise intest plan creation, simulation environment setup, debugging, and coverage closure. Leadverification planning and executionfor fabric‑level and full‑chip designs, ensuring thorough validation across all design hierarchies. Collaborate witharchitecture, firmware, and design teamsto develop detailed test plans that align with design specifications and performance goals. Architect and implement test benchesfrom scratch using System Verilog/UVM methodologies. Developconstrained‑random stimulus generation, intelligent checkers, scoreboards, and assertions to ensure design correctness and coverage completeness. Create and maintainscalable verification flows, including automated regression and coverage‑driven methodologies. Contribute tocode reviews, feature verification tracking, and structured agile sprint processesto drive verification excellence. Skills SoCUVMHealth, Dental and Vision Insurance 401kSeniority level Mid‑Senior level Employment type Contract Industry Semiconductor Manufacturing Referrals increase your chances of interviewing at Triple Crown by 2xGet notified about new Design Specialist jobs in San Jose, CA.