Senior SoC Verification Engineer - UVM & SystemVerilog

TechDigital Group seeks an experienced ASIC Verification Engineer to own end-to-end verification across multiple design blocks. You will develop and maintain testbenches, sequences, agents, and scoreboards using SystemVerilog and UVM from scratch. You will execute directed and constrained tests, debug deeply, and drive coverage closure for complex networking silicon and interconnect ASICs. Strong collaboration with customer teams is essential.