Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up

A tech company in Cupertino is seeking an experienced ASIC/VLSI Design Engineer to design innovative communication systems. The role involves collaboration with multiple teams, RTL coding, and optimization of design for performance. Candidates should have over 5 years in digital design with strong Verilog/System-Verilog skills and educational background in electrical or computer engineering. This position allows creativity and independence in a cutting-edge environment.