ASIC Physical Design Engineer (Hybrid)
mentium technologiesSanta Barbara, CA
3 days ago
Industries
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Other Electronic Component ManufacturingAbout the role
Mentium Technologies Inc. is seeking an experienced and highly motivated Physical Design Engineer to join our ASIC/SoC design team. In this role, you will be responsible for the physical implementation of complex ASIC designs from synthesis through place and route, DRC/LVS and tapeout. You will work closely with RTL designers, architects and OSAT, foundry partners to ensure high-quality, timing-clean, and manufacturable silicon. This role offers an exciting opportunity to learn and work on cutting-edge vision AI accelerators, machine and deep learning algorithms, and make a meaningful impact on the development of a co-designed robust, client-facing hardware-software library. This role requires strong expertise in physical implementation methodologies, optimization techniques, and industry-standard EDA tools.
Key Responsibilities:
Perform full-chip and block-level physical design, including: Synthesis, Design-for-Test, Collateral setup / Library preparation, Floorplanning and power planning, Placement and clock tree synthesis (CTS), Routing and post-route optimization, and Static Timing Analysis and Closure Drive timing closure across all corners and modes (setup/hold, SI, IR/EM)Develop and refine physical design flows and methodologies Develop DFT flows and integrate DFT IPCollaborate with front-end, and verification teams for design integration Analyze and resolve congestion, timing, and power issues Perform physical verification (DRC/LVS/antenna)Support tapeout activities and post-silicon debugging when required Evaluate and integrate third-party IP and tools into physical design flows Automate repetitive tasks using scripting (Python, tcl, shell)
Required Qualifications:
PhD/MS/BS in Electrical Engineering, Computer Engineering, or equivalent 3+ years of ASIC physical design experience Strong understanding of: CMOS process technology Timing constraints, timing analysis and closure techniques Power integrity and signal integrity fundamentalsDRC and LVS debug Hands-on experience with industry EDA tools such as: Synopsys Design Compiler / ICC2 or Fusion Compiler Prime Time StarRCExperience with Synthesis including DFT (scan, JTAG, MBIST, LBIST)Experience with full-chip or large block implementation Strong debugging and problem-solving skills Silicon-proven tapeout experience Key Attributes Detail-oriented with strong analytical skills Effective communicator in both written and verbal contexts Self-driven with the ability to manage multiple priorities Process-oriented with a focus on continuous improvement Ability to work independently and collaboratively Why Join Mentium? At Mentium, you'll be at the forefront of vision AI technology, working alongside a talented team dedicated to innovation. We offer a collaborative environment where your contributions directly influence the development of cutting-edge solutions. Join us to make a meaningful impact in the field of vision AI.
Benefits:
Competitive compensation packages Opportunity to work on diverse, cutting-edge AI projects across a range of industries.401(k)Flexible PTOFull PPO medical, dental, and vision insurance coverage
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JOB OVERVIEW
Experience level
Lead
Location
Santa Barbara, CA
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
3 days ago
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