Senior Technical Architect

Job Summary: Leads block-level and top-level physical implementation, driving design closure from netlist to GDS while coordinating cross-functional teams. Also owns full-chip integration activities.

Key Responsibilities: Manage floorplanning, placement, CTS, routing, and signoff closureDrive PPA (Power, Performance, Area) optimizationFull-chip assembly and hierarchical integrationResolve timing, congestion, IR, EM, DRC/LVS issuesCoordinate with RTL, STA, DFT, Package, and Verification teamsTape-out planning and executionMentor physical design engineersSkillRequirementsStrong expertise in Synopsys ICC2/Fusion Compiler or Cadence InnovusAdvanced floorplanning and partitioning knowledgeTiming closure expertiseFull-chip integration and hierarchical design methodologiesTCL, Perl, Python scriptingExcellent debugging and stakeholder management skillsExperience with advanced process nodes (16nm and below preferred)