Sr. Staff Memory Design Engineer

MediaTek’s advanced Memory Design team in San Jose is looking for a high-performance senior memory design engineer to define and design custom memory and circuits for next generation ASICs for Cloud AI and Data center applications. Collaborate closely with product and architecture teams to design TCAM, SRAM, CPU caches with different PPA requirements for Cloud AI ASICs. Advance DTCO optimization techniques in circuits and architecture to gain PPA beyond process entitlement. Design dual rail custom memories from start to finish to meet customer PPA spec. Mentor, guide, and direct other designers, while being hands-on in digital circuit design, especially targeting memories. Highly organized and independent design engineer who can multi-task and closely collaborate with worldwide design and CAD teams. Main Requirements and Qualifications 10+ years of hands-on experience in design of embedded memories (SRAM, TCAM) for high performance processors or ASICs in advanced nodes. PhD or MS in Electrical Engineering. Strong circuit and SRAM/TCAM design background in N2P, N3P process nodes. Strong understanding of Digital Circuit design techniques to build complex digital logic cells with dynamic and static circuits to perform compute functions in advanced technologies. Exposure to complete design cycle of SRAM memory and compiler development Supervise layout engineers and review layout for optimality in advanced nodes. Should have the ability to come up with comprehensive design verification plans, silicon bring-up plans for high-performance embedded memories. Experience in using industry standard schematic entry tools, advanced transistor level simulators, STA such as PrimeTime and Nanotime. Experience with LEC tools (ESPCV) Ability to review and coordinate layout activities Silicon debug and bring up experience is required. Working knowledge of scripting in Perl/Python Willingness to collaborate closely with cross functional teams across the globe.