Lead Mixed-Signal Verification Engineer (Tapeout)

Nexperia's Integrated Circuit Solutions (ICS) Group seeks a highly motivated Mixed Signal Design Verification Engineer to validate analog and mixed-signal IC designs before tapeout. You will lead pre-Si verification, develop environments, and collaborate with design and systems teams to ensure silicon meets specs and is manufacturable. The role requires strong Verilog/SystemVerilog/UVM experience, Cadence Virtuoso proficiency, scripting, and excellent communication.