Senior SRAM Layout Architect - CMOS 5nm/3nm
dgn technologiesSanta Clara, CA
Senior SRAM Layout Architect - CMOS 5nm/3nm
dgn technologiesSanta Clara, CA
yesterday
Industries
Semiconductor and Related Device ManufacturingElectronic Computer ManufacturingPrinted Circuit Assembly (Electronic Assembly) ManufacturingAbout the role
DGN Technologies is seeking an experienced layout engineer to lead custom IC layout for SRAM and memory IP in advanced CMOS nodes. You will own floorplanning, routing, and top-level verification in collaboration with circuit, CAD, and foundry teams.
You will mentor engineers, advance layout methodologies, and ensure memory IP delivery meets tight reliability and performance targets in cutting-edge process nodes (5nm/3nm and below).
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JOB OVERVIEW
Experience level
Senior
Location
Santa Clara, CA
Occupation
Electronics Engineers, Except Computer
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday
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