Principal SerDes/PHY Verification Lead
astera labsSan Jose, CA
Principal SerDes/PHY Verification Lead
astera labsSan Jose, CA
9 days ago
Industries
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Electronic Computer ManufacturingAbout the role
Astera Labs is hiring a Principal Design Verification Engineer to own the functional verification of our high-speed SerDes/PHY IP—the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success at the analog/digital boundary.
You will partner with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks used in PCIe Gen 6/Gen 7,
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JOB OVERVIEW
Experience level
Lead
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
9 days ago
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