Senior Digital Engineer

Responsibilities: Architect and design low-power digital circuits for mixed-signal data conversion and power management Integrate RTL at block and top level and run simulations Contribute to mixed-signal design flow: architecture, partitioning, RTL Verilog/SystemVerilog, timing constraints, synthesis, LINT/CDC/RDC/UPF Collaborate with P&R to meet timing, area, and power targets Support DFT strategy and test-case development, top-level test-bench debugging Verify RTL and gate-level simulations and develop AMS/behavioral models with analog team Create design documents and participate in design reviews Perform silicon evaluation and implement engineering changes when needed Travel domestically or internationally on short notice Communicate with wider organization across silicon development stages

Key requirements: 5+ years of digital design experience in wireless handheld, data conversion, or power management Bachelor-level degree in Electrical Engineering, Electronics, Computer Engineering, Computer Science or related discipline Fluent in Verilog/SystemVerilog RTL for digital CMOS design Strong understanding of ASIC design methodology Strong understanding of Lint, CDC & RDC tools Strong understanding of block- and chip-level verification techniques Proven ability to debug RTL and gate-level simulations Excellent written and verbal English Willingness to travel on short notice Ability to work independently and collaboratively team collaboration effective communication problem solving and debugging Verilog / SystemVerilog RTL ASIC design methodology LINT, CDC, RDC tooling