Senior Physical Design Engineer: End-to-End ASIC/FPGA

Roguebeam is seeking a Senior Physical Design Engineer to own block- and chip-level implementation from netlist to GDS, with FPGA P&R support, for phased-array solutions. You will floorplan, place, clock, route, and sign off silicon that carries digital beamforming and adaptive processing. You will collaborate end-to-end on timing, CTS, and verification, integrating memories, high-speed interfaces, and DFT structures.