Senior Analog Mixed-Signal Verification Engineer

What You’ll Do: Lead verification planning and execution at the block, subsystem, and full-chip levels. Develop reusable verification environments, behavioral models, checkers, assertions, and scoreboards using Verilog-AMS, SystemVerilog, UVM, and Real Number Modeling (RNM).Connect digital and mixed-signal verification flows to verify interactions between analog circuitry and digital control. Verify PMIC functions including monitoring, telemetry, diagnostics, configuration, protection, power sequencing, and fault management. Drive constrained-random testing, mixed-signal simulation, regression automation, coverage analysis, debugging, and verification signoff. Track requirements coverage, resolve defects, and manage verification milestones. Improve simulation efficiency and verification reuse across projects while providing technical guidance to junior engineers. What You’ll BringMaster’s degree in Electrical Engineering, Computer Engineering, or a related field. At least 10 years of analog and mixed-signal IC verification and development experience, including technical leadership. Strong knowledge of analog and mixed-signal circuits, including PMICs, DC-DC converters, LDOs, ADCs, DACs, PLLs, voltage references, bandgaps, and sensor interfaces. Expertise in Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and RNM.Experience building behavioral models and reusable, coverage-driven verification environments. Proficiency with industry-standard Cadence, Synopsys, and Siemens EDA tools. Scripting experience with Python, Perl, Tcl, or Shell. Strong analytical, communication, and cross-functional collaboration skills. Experience with formal verification, low-power verification, and requirements traceability is highly desirable. Interested? Contact Jan Mohondro at Analog Group to discuss the opportunity.