VP, Physical Design & Chiplet Architecture
astera labsSan Jose, CA
VP, Physical Design & Chiplet Architecture
astera labsSan Jose, CA
yesterday
Occupations
Computer Hardware EngineersElectronics Engineers, Except ComputerArchitectural and Engineering ManagersIndustries
Semiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)Other Electronic Component ManufacturingAbout the role
Astera Labs seeks a VP of Physical Design to lead full-chip physical design for next-generation switching products with UCIe and UALink. You will drive multi-die architectures, tapeouts, and performance targets in collaboration with architecture, digital design, packaging, and silicon teams.
You will mentor a growing PD team, ensure robust timing closure, power and area optimization, and lead efforts across 7nm or below node implementations.
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JOB OVERVIEW
Experience level
Manager
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Semiconductor and Related Device Manufacturing
Posted
yesterday
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