ASIC Design Engineer - Networking/ DPU/ AI Systems

THE TEAM: Our group, NTSG, develops advanced system solutions that combineASIC, hardware, and softwareto enable next-generationAI networking workloads. We are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production.

THE ROLE: We are seeking aSenior ASIC Design Engineer with seasoned experiencein the development of high-speed, complex ASICs. The ideal candidate has hands‐on experience across the full ASIC development cycle — fromRTL architectureanddesignthroughtapeout, silicon bring‐up, and mass production. THE PERSON:We are seeking aSenior ASIC Design Engineer with seasonedexperiencein the development of high-speed, complex ASICs. The ideal candidate has hands‐on experience across the full ASIC development cycle — fromRTL architectureanddesignthroughtapeout, silicon bring‐up, and mass production.

KEY RESPONSIBILITIES: Architect and design key blocks for next-generationDPU ASICstargeting AI networking workloads Contribute across the full ASIC development lifecyclearchitecture definitionmicroarchitecture and RTL designdesign reviewsimplementation supporttapeoutsilicon bring‐upproduction ramp and mass deployment support Collaborate on advanced network processing engines, includingP4-based, protocol-independent packet processing solutions Design and implement high‐speed, complex ASIC blocks for networking and data movement applications Work closely with verification, modeling, software, and hardware teams to ensure functional correctness and system‐level performance Debug and resolve issues across simulation, emulation, lab bring‐up, and post‐silicon phases Contribute to performance, power, and area optimization Support integration of ASIC IPs into larger SoC and system architectures Produce high‐quality design documentation and participate in technical reviewsREQUIRED QUALIFICATIONS:Seasoned ASIC design experience Proven hands‐on experience developinghigh-speed, complex ASICsStrong experience across the complete ASIC development cycle, fromRTL architecture to tapeout to massproduction Solid background in networking and packet‐processing architecturesExperience collaborating across: Verification ModelingSoftwareHardware/system teams Strong RTL design skills in: Verilog SystemVerilogStrong programming skills in: C/C++Scripting experience in: